Field of the Invention
The invention relates to jitter and more particularly to dealing with jitter that contains large jitter due to packet delay variations relative to random jitter.
Description of the Related Art
Optical transport networks (OTNs), broadcast video, and other applications use timing signals as part of the system to transport payloads. Such timing signals include a signal component caused by random or thermal related jitter. Thus, timing signals for one part of the system are nominally, but not exactly the same as timing signals for another part of the system. Phase-locked loops (PLLs) have traditionally been used to deal with the random jitter. However, transport networks may also insert systematic jitter in timing signals by, e.g., inserting gaps in clocks to align input and output data. For example, assume data is being received at a network node at a rate of 1 Gb/s but is being transmitted from the node at a slower rate of 1% less than 1 Gb/s. One way to deal with that rate difference is to skip pulses or insert gaps into the timing signal (nominally 1 Gb/s) transmitted with the slower transmitted data. Thus, skipping clock pulses can be used to account for slightly different input and output data rates.
Use of gapped clocks is a convenient technique used in communication systems to pass timing and frequency information. The technique has the advantage of being a simple and universal interface where frequency/timing information is embedded within the clock signal. The drawback of using the gapped clock technique, however, is the jitter caused by the gaps for the downstream system. Since the gaps are inserted by OTN mappers/de-mappers, there is no noise shaping, nor any pattern control of these gap insertions. To reduce the clock jitter for downstream systems, very low bandwidth jitter cleaning devices (e.g. below 10 Hz) are typically used to filter out the jitter/wander caused by clock gaps. Since the gap patterns are very unpredictable and difficult to model and characterize, system performance cannot be guaranteed. That is one reason gapped clock techniques are not widely used despite the cleanness in system partitioning afforded by gapped clocks. Other drawbacks of gapped clock use is that low bandwidth jitter cleaning, which is sensitive to temperature fluctuations, has excessive system response latency. In addition, gapped clock use increases system cost due to the need for very low bandwidth jitter cleaning devices.
Large jitter can also be caused by wander in packet-based timing systems. Wander filtering is commonly needed in packet-based timings networks such as described in Recommendation ITU-T G.8265.1/Y.1365.1 (“Precision time protocol telecom profile for frequency synchronization”), Recommendation ITU-T G.8263/Y.1363 (2012—Amendment 2 (“Timing characteristics of packet-based equipment”); Recommendation ITU-T G.8261/Y.1361 (“Timing and synchronization aspects in packet networks”). Very low frequency wander filtering to address wander in packet-based timing networks is challenging and costly. Due to large packet delay variation (PDV), especially after more than 10 network hops, a very low loop bandwidth needs to be used to filter out jitter/wander. For example, a loop bandwidth of 1 mHz (where m is milli) may be used. Because of the long time constant associated with a 1 mHz loop bandwidth, the base frequency reference in the PLL needs to be ultra stable to meet the system specifications regardless of the PLL technology.
Traditionally, as shown in FIG. 4, very low frequency wander filtering requires an ultra-stable local reference clock from an oven controlled crystal oscillator (OCXO) 401, which is supplied as a local reference to a very low bandwidth (e.g., 1 mHz) PLL 403 implemented using e.g., direct digital synthesis (DDS) or as a digital PLL. The very low bandwidth PLL 403 receives time stamps 405 associated with Internet Protocol (IP) packets and supplies a clock signal 409 after wander filtering. Such a solution can be expensive due the OCXO cost. For example, the costs of oven controlled crystal oscillators (OCXO) required to provide ultra stability, e.g., Stratum 2 or 3E OCXOs, dominate the synchronization costs of the system illustrated in FIG. 4 and may be in the range of $50-$100. In addition, it can take a long time, e.g., hours, for the low bandwidth PLL to respond.
Referring to FIG. 5, an exemplary timing diagram illustrates that packet delay may be present in the timing derived from time stamps 405 and can increase with network congestion 501 and decrease with lighter traffic 503. That is, during congestion a packet can take longer to reach its destination resulting in a greater difference between the time stamp associated with the transmitted packet and the arrival of the time stamp at its destination. Thus, as shown in FIG. 5 wander jitter may be higher during congestion. Note that random jitter is still present in the system.